MODEL=mipspipe
BENCH=bench
EXE=$(MODEL).exe
COMPILER=vcs
TIMESCALE=-timescale=10ns/10ns
VERSION=+v2k
TABLE=pli.tab
VCD=+define+VCD_SUPPORT_ON
LINT=+lint=all,noVCDE
DESIGN=../rtl/*.v
VERIF_LANG=.c
HDL=.v
LIB_DIR=/sim/synopsys/synthesis/dw/sim_ver/
LIB_EXT=+libext+.v
SEED=+tb_seed+
PARAMS=params.cfg

.PHONY: help

help:
	@echo "The following make targets are supported:" ;\
	echo " bench  - builds the testbench";\
	echo " design - builds the design";\
	echo " expand - expands veritedium directives (autoargs, inst etc.)";\
	echo " indent - automatically indents verilog and c files" ;\
	echo " stress - launch random testing";\
	echo " run - launch one random test";\
	echo " view - view the waveform";\
	echo " clean  - cleans testbench and intermediate files" ;\
	echo " refresh - cleans the testbench and intermediate files and re-expands the design";\
	echo " help   - show this information";\

bench: 
	$(COMPILER) $(VERSION) $(TIMESCALE) -P $(TABLE) $(VCD) -PP $(LINT) -y $(LIB_DIR) +incdir+$(LIB_DIR) $(LIB_EXT) $(DESIGN) $(BENCH)$(HDL) *$(VERIF_LANG) -o $(EXE)

indent:
	emacs --batch ../rtl/*.v -f verilog-batch-indent
	indent -linux *.c *.h
	rm *~

expand:
	emacs --batch ../rtl/MemoryStageWithRegisters.v -f verilog-batch-delete-auto -f save-buffer
	emacs --batch ../rtl/MemoryStageWithRegisters.v -f verilog-auto -f save-buffer
	rm *~

design: 
	$(COMPILER) $(VERSION) $(TIMESCALE) -P $(TABLE) $(VCD) -PP $(LINT) -y $(LIB_DIR) +incdir+$(LIB_DIR) $(LIB_EXT) $(DESIGN) -o $(EXE)

run: 
	./$(EXE) -cm +tb_cfgfile+$(PARAMS)

stress:
	for seed in `./count.py 100`; do ./$(EXE) $(SEED)$$seed; done

view:
	dve -vpd vcdplus.vpd &

clean:
	rm -rf *.o *~ *.vpi *.vvp *.vcd simv* csrc DVEfiles *.exe* *.vpd *.key *.dump

refresh:
	make clean
	make expand
